1. Field of the Invention
The present invention relates to a semiconductor device and a method for the preparation thereof. Particularly, the invention relates to a high-voltage semiconductor integrated circuit and a method for the preparation thereof. More particularly, the invention relates to a semiconductor device comprising a substrate and, formed thereon, an epitaxially grown layer having a flat surface but being partially different in the thickness, and a method for the preparation thereof.
2. Description of the Prior Art
A conventional semiconductor device is illustrated in FIG. 1. In the conventional integrated circuit, isolation is accomplished by applying a reverse bias to a PN junction and utilizing reverse characteristics of a PN diode. Accordingly, the upper limit of the breakdown voltage of the isolation-collector junction is controlled by the breakdown voltage of the PN junction. In FIG. 1, reference numeral 11 represents a semiconductor substrate of the P or N conductor type, reference numeral 12 represents a highly impurity-doped buried layer of the N or P conductor type, and reference numeral 13 represents a highly impurity-doped buried layer of the P or N conductor type. Reference numeral 14 represents an epitaxially grown semiconductor layer of the N or P type having a thickness t.sub.EP, and reference numeral 15 represents a highly doped P or N type diffusion layer for isolation. Reference numeral 16 represents a silicon oxide film (SiO.sub.2 film). In other FIGS. described hereinafter, these reference numerals represent the same elements. In general, it is considered that the following methods are effective for increasing the breakdown voltage of the planar type PN junction:
(1) To further reduce the impurity concentration in the lowly impurity doped region. PA1 (2) To increase the diffusion depth in the diffusion layer. PA1 (3) To form external elements such as a field plate FP and a field limiting ring FLR around the diffusion layer 32 as shown in FIG. 3.
In general, the diffusion layer 15 expands substantially in the circular form as seen from the sectional view of FIG. 2. Accordingly, if a reverse bias is applied to this PN junction, the intensity of the electric field in this circular portion is increased, and the breakdown voltage is determined by this circular portion. As the diffusion depth of the diffusion layer is increased, the concentration of the electric field in this circular portion is weakened, and hence, the breakdown voltage is improved.
Problems caused when the foregoing means are applied to the conventional integrated circuit having a structure as shown in FIG. 1 will now be discussed.
The resistivity and thickness of the epitaxially grown N type layer are determined by the breakdown voltage of a transistor formed therein. The voltage BV.sub.CEO between the collector and emitter of the transistor is determined from a maximum voltage V.sub.CCMAX applied to the circuit (in general, the relation of V.sub.CCMAX =BV.sub.CEO is established), and the breakdown voltage BV.sub.CBO between the base and collector is determined from the current gain h.sub.FE and BV.sub.CEO (in general, the relation of ##EQU1## is established). Since BV.sub.CBO is the breakdown voltage of the PN junction between the base and collector, the minimum resistivity .rho..sub.EPMIN of the epitaxial layer is determined from the value of BV.sub.CBO. In general, a value .rho..sub.EP higher than .rho..sub.EPMIN is set appropriately from the viewpoint of the deviation of the diffusion depth caused in the preparation steps and the influences of the surface.
When the value .rho..sub.EP is thus set, the thickness t.sub.EP of the epitaxial layer is then determined. The minimum value t.sub.EPMIN of this thickness corresponds to the width of a depletion layer which extends from the base-collector junction toward the epitaxial layer when a maximum voltage is applied in the state where the resistivity is at the maximum value .rho..sub.EPMAX, and the thickness t.sub.EP is determined in view of the deviation caused in the preparation steps.
From the foregoing illustration, it will readily be understood that in order to increase the breakdown voltage, it is necessary to heighten .rho..sub.EP and increase t.sub.EP. From FIG. 1, it will readily be understood that if t.sub.EP is increased, it is necessary to increase the diffusion depth of the diffusion layer 15 of the P.sup.+ type for isolation. When the diffusion depth is increased, expansion of the diffusion layer 15 for isolation in the lateral direction is increased as shown in FIG. 2 and the occupying area of the diffusion layer is increased. For example, in case of an integrated circuit having a breakdown voltage of 150 V, t.sub.EP is about 35 .mu.m and .rho..sub.EP is about 15 .OMEGA.-cm, and even if isolation is accomplished by the diffusion layer and buried layer as shown in FIG. 2, the diffusion depth x.sub.1 of the layer 15 is about 25 .mu.m and an additional area corresponding to this value becomes necessary for isolation. Further, as a result of increase of the .rho..sub. EP value, the expansion x.sub.2 of the depletion layer 21 shown in FIG. 2 becomes about 30 .mu.m, and therefore, an additional area corresponding to 30 to 40 .mu.m is necessary for the isolation region as compared with a low breakdown voltage integrated circuit.
When a high breakdown voltage integrated circuit is actually prepared, in general, the number of isolation islands on which elements actually requiring a high breakdown voltage are formed is usually small. Also the area necessary for such low breakdown voltage isolation is substantially the same as described above, and such increase of the area annuls the significance of an integrated circuit from the economical viewpoint.
The problem concerning low breakdown voltage portions is that the series resistance r.sub.SC of the collector of the transistor is greatly increased because .rho..sub.EP is heightened and the thickness t.sub.EP is increased. For example, the emitter area of a transistor customarily used for a low breakdown voltage integrated circuit is about 20 .mu.m.times.20 .mu.m, and .rho..sub.EP is 1.5 .OMEGA.-cm and t.sub.EP is about 10 .mu.m. If it is intended to realize a transistor having the same r.sub.SC value under the above-mentioned conditions of .rho..sub.EP =15 .OMEGA.-cm and t.sub.EP .perspectiveto.35 .mu.m, it is necessary to increase the emitter area. Namely, an emitter area of 120 .mu.m.times.120 .mu.m, 35 times the above emitter area, becomes necessary. Accordingly, realization of an integrated circuit becomes difficult from the economic viewpoint.
As means for overcoming the foregoing disadvantages, there has been proposed a structure shown in the sectional view of FIG. 4 (see Japanese Patent Publication No. 48955/1976). This structure is characterized in that the thickness of the epitaxial layer 14 differs in a high breakdown voltage element-forming portion 14-1 and a low breakdown voltage element-forming portion 14-2 and the diffusion layer 15 for isolation can be formed in the thin portion. In this structure, since a low breakdown voltage transistor is formed in the thin portion of the epitaxial layer, the emitter area necessary for maintaining r.sub.SC at the same level as in a low breakdown voltage integrated circuit should naturally be decreased as compared with the emitter area in the structure shown in FIG. 1.
As one method for preparing a semiconductor integrated structure as shown in FIG. 4, there can be mentioned a method comprising the steps of (1) etching a predetermined region of a substrate to form a substrate having a dent 41, (2) forming a semiconductor layer only on the dent of the substrate by selective epitaxial growth and (3) forming a semiconductor layer on the entire surface by second epitaxial growth, whereby an integrated circuit comprising a substrate and, formed thereon, an epitaxially grown layer having a flat surface but differing in the thickness can be prepared (see Japanese Patent Publication No. 48955/1976).
According to this method, however, the epitaxial growth should be conducted two times and procedures of the selective epitaxial growth at the step (2) is complicated. Therefore, the method as a whole is not simple.
As another method for preparing a structure as shown in FIG. 4, there can be mentioned a method comprising (1) etching a predetermined region of a substrate 11 to form a substrate having a dent 41, (2) forming a semiconductor layer on the entire surface of the substrate inclusive of the dent by epitaxial growth, and (3) forming a mask on the bottom face of a secondary dent formed on the epitaxially grown layer by transfer of the dent 41 of the substrate and flattening the surface of the epitaxially grown layer by etching (see Japanese Patent Application Laid-Open Specifications No. 43369/77 and No. 69587/77).
However, since in conventional semiconductor devices, a dent of a rectangular shape having sides parallel to the crystal axis &lt;110&gt; is formed, according to this method, in many cases, the surface of the epitaxially grown layer is not sufficiently flattened and convexities are readily formed around the mask of the secondary dent. Accordingly, etching or mechanical polishing should be further conducted for flattening the surface. Therefore, the method as a whole is complicated.